The present invention relates to frequency dividers and, more particularly, to variable frequency dividers for dividing clock frequency signals to obtain lower frequency signals.
Clock signals are used in electronic systems to synchronize processing between electronic components within the systems. The clock signals are typically generated by or based on a relatively high frequency clock signal produced by a system clock. Frequently, components within the system require clock signals having a lower frequency than the high frequency clock signal. Frequency dividers are used to reduce the high frequency clock signal to lower frequency signals required by these components.
Conventionally, counter based frequency dividers which generate a pulse after each counting period are used to divide a high frequency clock signal by an integer value. These counters are xe2x80x9cORxe2x80x9ded together to produce rational rate multipliers (RRM) capable of dividing high frequency clock signals by rational numbers, e.g., frequency division by three-fifths (⅗) or other rational numbers. The RRMs produce a series of pulses which are capable of non-integer frequency division on average, however, their momentary frequency varies over time and their duty cycles may be uneven, i.e., other that 50%. A changing momentary frequency is when the period of a signal changes between pulses and an uneven duty cycle is when the duration of a clock pulse is more or less than half the clock""s period. Due to the sensitivity of some system components, a constant momentary frequency with a near 50% duty cycle is desirable.
FIG. 1 depicts illustratively a clock signal 10 and a non-uniform divided clock signal 12 produced from the clock signal 10 by a frequency divider such as an RRM. An RRM used to produce the divided clock signal 12 in the present illustration utilizes three counters xe2x80x9cORxe2x80x9ded together in a conventional manner. The RRM operates by loading each of the counters with an appropriate counting period and delay. The counting period determines the distance between pulses for each individual counter and the delay spreads out the pulses of the counters when combined. For example, if the RRM was to divide the clock signal 10 by ⅗, three counters could be employed to generate three pulses 16, 18, and 20 spread over a period of five clock cycles 14. In this example, each counter is configured to count for five cycles and produce a pulse. In addition, upon initialization, the first counter produces the first pulse 16 with no delay, the second counter produces the second pulse 18 after a one clock cycle, and the third counter produces the third pulse 20 after a three clock cycle delay. In this manner, the RRM will produce 3 pulses every five clock cycles 14 with the pulses spread over the five clock cycles 14 and, therefore, will divide the clock signal 10 by ⅗.
As depicted in FIG. 1, although the average frequency of the divided clock 12 is ⅗ the frequency of the clock signal 10, the momentary frequency of the divided clock 12 varies over time. For example, the period 22 containing the first pulse 16 is the same as the period of the clock signal 10 and, therefore, the divided signal will have the same momentary frequency as the frequency of the clock signal 10. However, periods 24 and 26 containing the first and second pulses 18 and 20 are twice the period of the clock signal 10 and, therefore, will have a momentary frequency which is half the frequency of the clock signal 10. In addition, the duty cycle of the divided clock signal 12 varies between approximately 50% for the first pulse 16 (see pulse width 28 versus period 22) and approximately 25% for the second pulse 18 (see pulse width 30 versus period 24). The varying momentary frequency and uneven duty cycle is a result of using pulses which are produced by the counters in the RRM as the pulses 16, 18, and 20 of the divided clock 12. Since the width of the pulses 16, 18, and 20 and the distance between them would have to change as the divisor of the RRM changes, it is difficult to maintain a constant momentary frequency and even duty cycle. This is due to inherent difficulties in changing the duration of the individual pulses produced by a counter and spreading the pulses over a specified period, e.g., the period of five clock cycles 14.
Since, as mentioned above, it is desirable to divide high frequency clock signals to obtain a specific, uniform lower frequency signal, and this is hindered by the capabilities of present frequency dividers which are capable generally of dividing by integers only or producing a signal having a momentary frequency or duty cycle which varies over time, there is a need in the industry for a stable, variable frequency divider able to divide high frequency clock signals with more precision than traditional integer based dividers. The present invention fulfills this need among others.
The present invention provides for a frequency divider and method for dividing a clock signal which overcome the aforementioned problems by producing an output which is based on counting intervals. In doing so, the present invention is able to divide an input frequency by multiples of half an integer with a constant momentary frequency while maintaining a duty cycle of approximately 50%.
One aspect of the present invention is a frequency divider for dividing a clock signal to produce a reduced frequency output signal. In a preferred embodiment, the frequency divider comprises a first configurable signal generator having an input for receiving the clock signal, a second configurable signal generator having an input for receiving the clock signal, a data source coupled to the signal generators making configuration data available to the first and second configurable signal generators based on instructions received at an instruction port, a sequencer generating the instructions based on outputs of the first and second configurable signal generators coupled between the first and second signal generators and the data source, and combining logic coupled to the outputs of the signal generators producing the reduced frequency signal.
Another aspect of the invention is a method for dividing a clock signal. In a preferred embodiment, the method divides a clock signal to generate a reduced frequency signal by generating a first signal comprising first and second counting intervals which are individually configurable and based on a rising edge of the clock signal, generating a second signal comprising third and fourth counting intervals which are individually configurable and based on a falling edge of the clock signal, and combining the signals to create the reduced frequency signal, wherein the output level of the reduced frequency signal changes after every counting interval.